Four operations on two bits, selected by two control bits. This is what a CPU does. Build a tiny 1-bit ALU — the capstone of the curriculum.
A 1-bit ALU takes two data bits (Input A, Input B) and two selector bits (Op Low, Op High), and emits one result bit. The selector picks which operation to run:
| Op High | Op Low | Operation |
|---|---|---|
| 0 | 0 | AND (A ∧ B) |
| 0 | 1 | OR (A ∨ B) |
| 1 | 0 | XOR (A ⊕ B) |
| 1 | 1 | NOT A (B ignored) |
A real CPU's ALU is just this shape writ wider: 8, 16, 32, or 64 bits instead of 1, and usually with addition and subtraction thrown in. But the structure is the same — compute everything in parallel, then MUX the one you want to the output.
and_result = A ∧ Bor_result = A ∨ Bxor_result = A ⊕ Bnot_result = ¬A(Op High, Op Low) that
picks one of those four results.A 4-to-1 MUX is a tree of three 2-to-1 MUXes:
and_result ─┐
├── 2:1 MUX (Op Low) ─┐
or_result ─┘ ├── 2:1 MUX (Op High) ── Output
│
xor_result ─┐ │
├── 2:1 MUX (Op Low) ─┘
not_result ─┘
When Op High = 0, the final MUX picks from {AND, OR} (chosen by
Op Low). When Op High = 1, it picks from {XOR, NOT}.
Place four Levers labeled Input A, Input B, Op Low, and Op High. Compute the four operation results, build the MUX tree from lesson 7, and send the final output to a Lamp labeled Output. Flip through combinations of op bits to see the ALU switch personalities.
If you haven't built a half or full adder yet, this one is doable but
large — give yourself room on the canvas, and use the redstone
patterns at /redstone if you want a gate-by-gate reference.
You've finished the combinational half of the curriculum — every gate, every adder, every multiplexer, every operation that's a pure function of its inputs.
The next three lessons cross the divide into sequential logic — circuits that remember:
Combine the ALU you just built with the registers you'll build next and you have, in miniature, a CPU. Everything else is composition.